Optical surface quality and molecular dynamics modelling of ultra-high precision optical silicon machining
- Authors: Abdulkadir, Lukman Niyi
- Date: 2019-04
- Subjects: Engineering design -- Data processing , Manufacturing processes -- Data processing , Mechatronics
- Language: English
- Type: Doctoral theses , text
- Identifier: http://hdl.handle.net/10948/66552 , vital:75601
- Description: Hard and brittle materials, such as silicon, silicon carbide etc., are widely used in aerospace, integrated circuit, and other fields due to their excellent physical and chemical properties. However, these materials display poor machinability owing to hardness, brittleness, non-linearity in machining process and complexities in selecting suitable machining parameters and tool geometry. These leads to low quality lenses due to subsurface damage and surface micro-crack. Additionally, it is experimentally very difficult to observe all nanoscale physical phenomena due to in-process measurement problems, inaccessible contact area of tool and workpiece, and the difficulty of surface analysis. With the use of molecular dynamics (MD) which is a comprehensive nanoscale modelling technique, proper selection of process parameters, tool geometry and online monitoring techniques, production of freeform optics is possible through Ultra-high precision diamond turning (UHPDT). Though, depending on view point, machinability in UHPDT may be in terms of tool wear rate, hardness, chip morphology, surface roughness, and other benchmarks. These situations have called for more insights, which on the long run will help to achieve high precision manufacturing with predictability, repeatability, productivity and high infrared (IR) optical quality. In this thesis, UHPDT of monocrystalline silicon at atomistic scale was conducted to investigate combined effects of edge radius, feed rate, cutting speed, depth of cut, rake and clearance angles hitherto not done so far. Using appropriate potential functions with the MD algorithm, comprehensive analysis of thermal effects, diamond tool wear, phase change, cutting forces and machining stresses (normal, shear, hydrostatic and von Mises) were carried out. Dislocation extraction algorithm (DXA) and radial distribution function (RDF) were used to evaluate dislocation nucleation, variations in bond lengths, microstructural transformation and represents structural changes in histogram form. Selected parameters for optical quality surface roughness were afterwards compared and optimized through response surface methodology (RSM) based on Box Behnken (BBD) and Taguchi L9 methods. The results indicated that, silicon atoms in the chip formation zone undergo high pressure phase transformation (HPPT) at high hydrostatic pressure and temperature.Silicon microstructure transformed from four-coordinated diamond cubic structure (Si- I) to unstable six-coordinated body-centered tetragonal structure (β-silicon) which then transformed to amorphous silicon atoms (a-Si) through amorphization. These resulted in plastic deformation and defects in the machining zone causing subsurface damage. Stress analysis indicated that the compressive stress in the machining zone (i.e. amorphous region) suppressed crack formation contributing to continuous plastic flow which is responsible for silicon ductile-mode cutting. Furthermore, formation of silicon carbide which constituted diamond wear was observed to be by sp3 - sp2 diamond carbon atom disorder and tribochemistry. The tribochemistry occurred through both multiphase and solid-state single-phase reaction between diamond tool and silicon workpiece at cutting temperatures above and below 959 K. Both the experimental findings and the simulation results reveal that, at edge radius less than uncut chip thickness, tool wear was more of rake wear than flank wear. Tool wear and kinetic friction reduced as the edge radius approached the uncut chip thickness while forces, stresses and SCE increased. When machining silicon at differentratio, silicon stress state, SCE, SSD, forces (reduced with increase in clearance angle), shear plane, chip velocity and chip ratio increased as edge radius and rake angle increased, while, kinetic friction, chip length and thickness reduced. The crystal lattice of the machined surfaces and subsurface deformed layer depth increased with increase in edge radius, feed and rake angle. Amongst all tested and analysed parameters, feed rate had the highest influence on surface quality while depth of cut showed the least. Acoustic emission was also monitored during machining and its results statistically analysed. The trends of the monitored acoustic emissions showed its capability to adequately represent and predict surface roughness results. Based on the developed simulation model a novel method for quantitative assessment of tool wear was proposed. The proposed model can be used to compare tool wear using graphitization and tribochemistry to decide the path and mode of the diamond tool wear. Finally, based on the experiment results and predictive model, a novel combination and hierarchical arrangement of the considered factors capable of suppressing tool wear and improve attainable machined surface roughness when turning hard-to-machine materials was proposed. , Thesis (D.Phil) -- Faculty of Engineering, the Built Environment, and Technology, School of Engineering, 2019
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- Date Issued: 2019-04
Design of a dedicated IFT microcontroller
- Authors: Himunzowa, Grayson
- Date: 2018
- Subjects: Feedback control systems , Automatic control , Engineering design -- Data processing
- Language: English
- Type: Thesis , Doctoral , DPhil
- Identifier: http://hdl.handle.net/10948/30017 , vital:30809
- Description: The design of a Dedicated IFT Microcontroller originated from the successful implementation of the Iterative Feedback Tuning (IFT) technique into the Digital Signal Processor microcontroller (DSP56F807C) at the University of Cape Town in 2006. However, implementation of the IFT technique on a general-purpose microcontroller is neither optimal, nor a cost-effective exercise, as most of the microcontroller peripherals remain unused, and drain energy for doing nothing. In addition, microcontrollers and DSPs are software-driven devices whose nature is sequential in executing algorithms, and hence have a significant effect on the bandwidth of the closed-loop control. To mitigate the said problem, the design of a Dedicated IFT Microcontroller is proposed in this thesis. To accomplish this goal, the preliminary task was to explore the IFT theory and its applications, followed by a review of the literature on FPGA design methodology for industrial control systems, Microcontroller design principles, and FPGA theory and trends. Furthermore, a survey of electronic design automation (EDA) tools and other application software was also conducted. After the literature review, the IFT was investigated exhaustively by applying it to three types of plants, namely: a DC motor, an oscillatory plant, and an unstable plant. Each of these plants were tested using three types of initial controllers, namely heavilydamped, critically damped and under-damped initial controllers. The plants were also tested by varying the amplitude of the reference signal, followed by using a single-step signal of constant amplitude of one volt. The intention of exploring all of these possibilities was meant to firmly expose the IFT boundaries of applicability, so that the final product would not be vulnerable to unnecessary post-production discoveries. The design methodology adopted in this research was a popular hierarchical and modular top-down procedure, which is an array of abstraction levels that are detailed as: system level, behavioural level, Register-Transfer Level (RTL) and Gate level. At system level, the Dedicated IFT Microcontroller was defined. Thereafter, at behavioural level, the design was simulated using VHDL, created by porting the LabView IFT code to the Xilinx EDA tool. At the RTL, the synthesisable VHDL code utilising fixed-point number representation was written. The compiled bit file was downloaded onto National Instruments (NI) Digital Electronics FPGA Board featuring iii the Spartan 3 series FPGA. This was tested, using a method known as simulation in the hardware. The key contribution of this thesis is the experimental validation of the IFT technique on FPGA hardware as it has never been published before, the work described in chapter four and five. The other contribution is the analysis of 1DOF IFT technique in terms of limitations of applicability for correct implementation, which is the main work of chapter three. This work could be used to explore other computational methods, like the use of floating-point number representation for high resolution and accuracy in numerical computations. Another avenue that could be exploited is Xilinx's recent Vivado methodology, which has the capacity for traditional programming languages like C or C++, as these have in-built floating-point number capability. Finally, out of this work, two papers have already been published by Springer and IEEE Xplore Publishers, and a journal paper has also been written for publication in the Control Systems Technology journal.
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- Date Issued: 2018